1. Technical Field
The present invention is directed generally toward a method and apparatus for implementing a dual-port static random-access memory in an integrated circuit.
2. Description of the Related Art
There are two basic types of semiconductor random-access memory (RAM) circuits in common use. Static random-access memory (SRAM) stores data by way of a feedback circuit. Dynamic random-access memory (DRAM) stores data as electrostatic charge on a capacitor. In general, RAM circuits are configured in two-dimensional arrays of individual memory cells, with each memory cell storing one bit. A word of data may be accessed from one or more memory circuits by addressing the cells that store the data by row and column addresses and reading or writing data to or from the addressed cells. In a typical SRAM array, each memory word is stored in a separate row and addressed by asserting a xe2x80x9cword line,xe2x80x9d while the individual bits of each word are read from and written to the memory array using xe2x80x9cbit lines.xe2x80x9d In a typical single-port memory array, all bit lines for a particular bit position are connected together. For example, all memory cells representing bit position 4 of a word typically share common bit lines, but have separate word lines. The generic term for word lines and bit lines is xe2x80x9caddress lines,xe2x80x9d as address lines are used for addressing individual memory cells.
Memory circuits may be single-port or multi-port memory circuits. Single-port circuits are capable of allowing access to a single memory location (i.e., one cell or a group of cells at a single memory address). Multi-port circuits allow two or more memory addresses to be accessed concurrently. Specifically, a xe2x80x9cportxe2x80x9d is a set of related address lines that together are sufficient to perform one memory access at a particular point in time. Thus, a single-port memory cell, which only has one port, is capable of supporting only one access at a time, while a dual-port memory cell, which has two ports, is capable of supporting two simultaneous memory accesses. Higher-order multi-port cells (e.g., three-port, four-port, etc. . . ), which support larger numbers of simultaneous accesses, are also possible.
FIG. 1 is a diagram of a typical six-transistor single-port complementary metal-oxide semiconductor (CMOS) SRAM circuit 100 as known in the art. SRAM circuit 100 is perhaps the most common circuit topology for a single-port SRAM. SRAM circuit 100 includes a flip-flop circuit, which is formed by cross-coupling two logic inverters formed by transistors Q1-Q4, and two pass-gate transistors (also called access transistors) Q5 and Q6.
Specifically, PMOS (p-channel MOS) transistor Q3 and NMOS (n-channel MOS) transistor Q1 form one CMOS inverter and PMOS transistor Q4 and NMOS transistor Q2 form another CMOS inverter. Referring to the inverter formed by transistors Q3 and Q1, the gates of transistors Q3 and Q1 are connected together to form an input node 110 to the inverter. The sources of transistors Q3 and Q1 are connected together to form an output node 112 of the inverter. The drain of transistor Q3 is connected to positive supply rail Vdd 106, making transistor Q3 the xe2x80x9cpull-upxe2x80x9d transistor of the inverter. The drain of transistor Q1 is connected to negative (or xe2x80x9clowxe2x80x9d) supply rail Vss 108, making transistor Q1 the xe2x80x9cpull-downxe2x80x9d transistor of the inverter. Transistors Q4 and Q2 are similarly configured as a CMOS inverter. In SRAM circuit 100, the CMOS inverter formed by transistors Q4 and Q2 is cross-coupled with the CMOS inverter formed by transistors Q3 and Q1. Thus, node 110, which is the input node of the inverter formed by transistors Q3 and Q1, forms the output node of the inverter formed by transistors Q4 and Q2, and node 112, which is the output node of the inverter formed by transistors Q3 and Q1, forms the input node of the inverter formed by transistors Q4 and Q2.
Nodes 110 and 112 are referred to as the xe2x80x9cinternal nodesxe2x80x9d of SRAM circuit 100. For the purposes of this document, the term xe2x80x9cinternal nodexe2x80x9d is defined as a data-storing node in an SRAM circuit. In the case of circuit 100, nodes 110 and 112, because they form part of the feedback loop of the cross-connected CMOS inverters (transistors Q1-Q4), are data-storing nodes and are, therefore, xe2x80x9cinternal nodes,xe2x80x9d for the purposes of this document.
Pass-gate transistors Q5 and Q6 are MOS transistors configured as switches. The gates of transistors Q5 and Q6 are connected to word line 102. The source and drain of pass-gate transistor Q5 are connected between bit line 104 and node 112. The source and drain of pass-gate transistor Q6 are connected between inverse bit line 106 and node 110. Pass-gate transistors Q5 and Q6 are turned on when word line 102 is selected (i.e., raised in voltage) and connect bit lines 104 and 106 to the flip-flop formed by transistors Q1-Q4. When pass-gate transistors Q5 and Q6 switch bit lines 104 and 106 into connection with internal nodes 110 and 112, the data stored by memory circuit 100 becomes available on bit line 104, and the complement of that data becomes available on inverse bit line 106, so reading from memory circuit 100 becomes possible. To write data to memory circuit 100, word line 102 is selected, the data to be stored is asserted on bit line 104, and the complement of that data is asserted on inverse bit line 106. Since transistors Q1-Q4 form a bistable circuit (i.e., a circuit with two stable states), asserting the new data on bit lines 104 and 106 results in putting this bistable circuit into the stable state associated with the stored data. When word line 102 is no longer asserted, transistors Q1-Q4 maintain the same stable state, and thus store the written data until power is no longer available from power supply rails 108 and 109.
FIG. 2 is a diagram of a typical dual-port memory circuit 200 that is based on the six-transistor single-port circuit 100 in FIG. 1. Dual-port circuit 200 uses two word lines 202 and 204 for each word and two sets of bit lines (bit lines 206 and 208 and bit lines 210 and 212) for each bit position. Dual-port circuit 200 contains the same configuration of six transistors (Q1-Q4) as single-port circuit 100, but includes additional pass-gate transistors Q7 and Q8, which connect additional bit lines 210 and 212 to the internal nodes, nodes 214 and 216. Thus, with two separate bit line-word line-pass-gate transistor combinations in each memory cell, dual-port operation is achieved.
FIG. 3 is a diagram showing how a typical SRAM memory array 300 is configured from individual memory cells. Memory array 300 is a single-port memory array (i.e., it consists of only single-port memory cells and supports only one memory access at a time), although multi-port memory arrays are also common. In memory array 300, words are arranged in rows, and bit positions are arranged in columns. For instance, word line 302 enables access to all of the bits in the memory word represented by that row, while word line 304 enables access to all of the bits in the succeeding memory word in the memory space provided by memory array 300.
Each column in memory array 300 represents a bit position within a word. Thus, bit line 306 and its complement bit line 308 represent a particular bit position, while bit line 310 and its complement bit line 312 represent the succeeding bit position. Note that all of memory cells corresponding to a particular bit position are connected to the same word lines. Thus, each individual memory cell in memory array 300 is accessed by row and column.
In xe2x80x9csystem on a chipxe2x80x9d (SoC) applications, where a complete system of components is manufactured on a single integrated circuit (IC), SRAM arrays, such as that depicted in FIG. 3, may serve any of a variety of functions. The six-transistor SRAM cell depicted in FIG. 1 (memory circuit 100) is regarded as being the most common SRAM cell currently in use in industry, since the six-transistor SRAM cell is fast and also suitable for high-density applications, where space in the IC layout is at a premium.
In many communications and networking applications, multi-port SRAM cells are often used, because they offer the capability of simultaneous memory access from multiple ports. The eight-transistor dual-port memory cell depicted in FIG. 2 is regarded as the most popular topology for a multi-port memory cell. Typically, the SRAM cells in any given memory array are individually designed at the silicon level to provide dedicated single-port or dual-port functionality. This allows the highest level of optimization and customization for density and performance.
In some applications, however, programmability, or at least simplicity of the design process, becomes a priority. When rapid turnaround time or ease of manufacturing is needed, a xe2x80x9cprogrammablexe2x80x9d IC, which provides a standardized, generic set of components, such as logic gates or memory cells, can be xe2x80x9cprogrammedxe2x80x9d to implement the desired functionality. Thus, rather than laying out each individual transistor circuit in the design, a designer can simply make or break connections between the standard, generic components in the IC to achieve the desired result. Many devices that are called xe2x80x9cprogrammablexe2x80x9d may be programmed using some sort of programming apparatus, such as an FPGA (field-programmable gate array) programmer device. Another form of xe2x80x9cprogrammingxe2x80x9d is xe2x80x9cmetal programming,xe2x80x9d in which one or more metal layers in the layout of an IC are used to form connections between the standard component. xe2x80x9cMetal programmingxe2x80x9d is useful for implementing IC designs that are to be commercially manufactured. In general, metal programming allows the designer the convenience of designing a circuit using a programmable device as a basis for the design, but xe2x80x9cmetal programmingxe2x80x9d is also rather conducive to mass manufacture, as the xe2x80x9cprogrammedxe2x80x9d part of the IC can simply be implemented as a layer in the usual fabrication process, rather than by having to xe2x80x9cbumxe2x80x9d the programmed part into the IC using a special programmer device.
As some applications require multi-port memory, while others do not, a designer must choose what kind of memory to use (i.e., single- or multi-port) in the application. As programmability can greatly simplify the design process of an IC, it would be desirable to program a memory array to act as a single-port or multi-port memory array, depending on the xe2x80x9cmetal programming.xe2x80x9d
The present invention provides a method and apparatus for providing dual-port capability to an SRAM array. The internal nodes of single-port memory cells are connected to each other through metal-layer programming to form a dual-port memory cell. In a preferred embodiment, a split word line design is used for each single-port memory cell, to facilitate dual-port memory access while minimizing the need for IC layout space. An additional benefit of the present invention is that it allows xe2x80x9cslicesxe2x80x9d of a memory array to be converted into dual-port memory, so as to allow both single-port and dual-port memory cells in the same memory array.